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Modeling of Jitter Characteristics for the Second Order Bang-Bang CDR | ||
| AUT Journal of Modeling and Simulation | ||
| مقاله 5، دوره 44، شماره 2، بهمن 2012، صفحه 37-45 اصل مقاله (605.28 K) | ||
| نوع مقاله: Research Article | ||
| شناسه دیجیتال (DOI): 10.22060/miscj.2012.128 | ||
| نویسندگان | ||
| Habib Adrangi؛ Hossein Miar Naimi | ||
| چکیده | ||
| Bang-Bang clock and data recovery (BBCDR) circuits are hard nonlinear systems due to the nonlinearity introduced by the binary phase detector (BPD). The specification of the CDR frequency response is determined by jitter tolerance and jitter transfer. In this paper, jitter transfer and jitter tolerance of the second-order BBCDR are characterized by formulating the time domain waveforms. As a result, a new equation is presented to obtain corner frequency. Also, the jitter tolerance is expressed in closed form as a function of loop parameters. The proposed method is general enough to be used for designing BBCDR. The analysis is verified using behavioral simulations in MATLAB. Simulation results demonstrate the validity of the result obtained by analytical equations. | ||
| کلیدواژهها | ||
| Clock and Data Recovery (CDR)؛ Bang-Bang Phase Detector (BPD)؛ Jitter Transfer and Jitter Tolerance | ||
| عنوان مقاله [English] | ||
| Modeling of Jitter Characteristics for the Second Order Bang-Bang CDR | ||
| چکیده [English] | ||
| Bang-Bang clock and data recovery (BBCDR) circuits are hard nonlinear systems due to the nonlinearity introduced by the binary phase detector (BPD). The specification of the CDR frequency response is determined by jitter tolerance and jitter transfer. In this paper, jitter transfer and jitter tolerance of the second-order BBCDR are characterized by formulating the time domain waveforms. As a result, a new equation is presented to obtain corner frequency. Also, the jitter tolerance is expressed in closed form as a function of loop parameters. The proposed method is general enough to be used for designing BBCDR. The analysis is verified using behavioral simulations in MATLAB. Simulation results demonstrate the validity of the result obtained by analytical equations. | ||
| کلیدواژهها [English] | ||
| Clock and Data Recovery (CDR), Bang-Bang Phase Detector (BPD), Jitter Transfer and Jitter Tolerance | ||
| مراجع | ||
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[1] J. K. Kim, J. Kim, G. Kim and D. K. Jeong, “A fully integrated 0.13-μm CMOS 40-Gb/s serial link transceiver,” IEEE J. Solid-State Circuits., vol. 44, no. 5, pp. 1510-1521, May. 2009. [2] N. Da Dalt, E. Thaller, P. Gregorius and L. Gazsi., “A compact triple-band low-jitter digital LC PLL with programmable coil in 130-nm CMOS,” IEEE J. Solid-State Circuits., vol. 40, no. 7, pp. 1482-1490, Jul. 2005. [3] Y. S. Seo, J. W. Lee, H. J. Kim, Ch. Yoo, J. J. Lee and Ch. S. Jeong, “A 5-gbit/s clock and data recovery circuit with 1/8-rate linear phase detector in 0.18-μm CMOS technology,” IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 56, no. 1, pp. 6-10, Jan. 2009. [4] B. Razavi, “Challenges in the design of high-speed clock and data recovery circuits,” IEEE Commun. Mag.,vol 40, no. 8, pp. 94-101, Aug. 2002. [5] N. Da Dalt, “Markov chains-based derivation of the phase detector gain in bang-bang PLLs,” IEEE Trans. Circuits and Syst. II, Exp. Briefs, vol. 53, no. 11, pp. 1195–1199, Nov. 2006. [6] B. Chun and M. P. Kennedy, “Statistical properties of first-order bang-bang PLL with nonzero loop delay,” IEEE Trans. Circuits and Syst. II, Exp. Briefs, vol. 55, no. 10, pp. 1016–1020, Oct. 2008. [7] S. Tertinek, J. P. Gleeson, and O. Feely, “Statistical analysis of first-order bang-bang phase-locked loops using sign-dependent random walk theory,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 57, no. 9, pp. 2367–2380, Sep. 2010. [8] S. Cheng, H. Tong, J. Silva-Martinez and A. I. Karsilayan, “Steady-state analysis of phase-locked loops using binary phase detector,” IEEE Trans. Circuits and Syst. II., vol.54, no.6, pp. 474-478, Jun. 2007. [9] R. C. Walker, “Designing bang-bang PLLs for clock and data recovery in serial data transmission systems” in Phase-locking in High Performance Systems, B. Razavi, Ed. Piscataway, NJ: IEEE Press, pp. 34–45, 2003. | ||
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