پیوندهای مفید
آمار
| تعداد نشریات | 8 |
| تعداد شماره‌ها | 419 |
| تعداد مقالات | 5,514 |
| تعداد مشاهده مقاله | 6,250,952 |
| تعداد دریافت فایل اصل مقاله | 5,422,372 |
New Insight on the Application of Binary Coded Chiliad (BCC) Encoding for Decimal Arithmetic | ||
| AUT Journal of Electrical Engineering | ||
| مقاله 5، دوره 53، شماره 1، شهریور 2021، صفحه 47-56 اصل مقاله (845.59 K) | ||
| نوع مقاله: Research Article | ||
| شناسه دیجیتال (DOI): 10.22060/eej.2020.19022.5379 | ||
| نویسنده | ||
| Morteza Dorrigiv* | ||
| Electrical and Computer Engineering Dept., Semnan University, Semnan, Iran. | ||
| چکیده | ||
| The densely packed decimal (DPD) encoding for secondary and primary storage of three binary coded decimal (BCD) digits is included in the IEEE 754-2019 standard for decimal floating-point arithmetic. Binary coded chiliad (BCC) representation of 3 BCD digits (i.e. radix-1000) will achieve equi-efficient packing. The primary advantage is BCC operands can be directly manipulated by arithmetic operations, while DPD operands have to undergo DPD-to-BCD and reverse conversions afore and ahead of each arithmetic operation. Therefore, we are interested in designing the arithmetic unit that receives BCC operands and produces BCC results, following previous BCC works. Compared to the equivalent BCD or other radix-10 arithmetic, prospects show that equally efficient arithmetic units are feasible for BCC arithmetic, as even better performance has been achieved in the case of addition. Therefore, we demonstrate the IEEE 754-2019 compatibility of the BCC Encoding in this paper. Consequently, for the DPD-to-BCD expansion and the reverse compression, the DPD-to-BCC converter, and the reverse blocks, we show the delay, area, and power dissipation. The findings show a substantial delay (83%), area (27%), and power (29%) overhead. However, as the number of conversions in the latter case is much less than the former, overall power dissipation is expected to decrease considerably. | ||
| کلیدواژه‌ها | ||
| Binary coded chiliad encoding؛ decimal computer arithmetic؛ IEEE 754-2019؛ densely packed decimal encoding؛ encoding conversion | ||
| مراجع | ||
|
[1] W. Buchholz, “Fingers or fists? (the choice of decimal or binary representation),” in Communications of the ACM, pp. 3–11, 1959. [2] M.F. Cowlishaw, “Decimal floating-point: algorism for computers,” in Proceedings of the 16th IEEE Symposium on Computer Arithmetic (ARITH '03), pp. 104–111, 2003. [3] W.S. Brown, and P.L. Richman, “The Choice of Base,” in Communications of the ACM, Vol. 12, pp. 560–561, 1969. [4] S.R. Carlough, A. Collura, S.M. Mueller, and M. Kroener, “The IBM zEnterprise-196 Decimal Floating-Point Accelerator,” in Proceedings of the 20th IEEE Symposium on Computer Arithmetic (ARITH '11), pp. 139–146, 2011. [5] C. Jacobi, and C. Webb, “History of IBM Z mainframe processors,” in IEEE Micro, pp. 1–10, 2020. [6] H.A.H. Fahmy, “Decimal Floating Point Number System,” in Embedded Systems Design with Special Arithmetic and Number Systems, Springer, 2017. [7] IEEE Standards Committee, “IEEE 754-2019 Standard for Floating-Point Arithmetic,” Revision of IEEE 754-2008, IEEE Computer Society Standard, pp. 1–84, 2019. [8] L.-K. Wang, M.J. Schulte, J.D. Thompson, and N. Jairam, “Hardware Designs for Decimal Floating-Point Addition and Related Operations,” in IEEE Transactions on Computers, Vol. 58, No. 3, pp. 322–335, 2009. [9] L.-K. Wang, and M.J. Schulte, “A Decimal Floating-Point Adder with Decoded Operands and a Decimal Leading-Zero Anticipator,” in Proceedings of the 19th IEEE Symposium on Computer Arithmetic (ARITH '09), pp. 125–134, 2009. [10] Á. Vázquez, and E. Antelo, “A High-Performance Significand BCD Adder with IEEE 754-2008 Decimal Rounding,” in Proceedings of the 19th IEEE Symposium on Computer Arithmetic (ARITH '09), pp. 135–144, 2009. [11] M.A. Erle, B.J. Hickmann, and M.J. Schulte, “Decimal Floating-Point Multiplication,” in IEEE Transactions on Computers, Vol. 58, No. 7, pp. 902–916, 2009. [12] C. Minchola, and G. Sutter, “An FPGA IEEE 754-2008 Decimal Floating-Point Multiplier,” in International Conference on Reconfigurable Computing and FPGAs, pp. 59–64, 2009. [13] C. Lichtenau, S. Carlough, and S.M. Mueller, “Quad Precision Floating Point on the IBM z13,” in Proceedings of the 23rd IEEE Symposium on Computer Arithmetic (ARITH '16), pp. 87-94, 2016. [14] A.A. Wahba, and H.A.H. Fahmy, “Area Efficient and Fast Combined Binary/Decimal Floating-Point Fused Multiply Add Unit,” in IEEE Transactions on Computers, Vol. 66, No. 2, pp. 226-239, 2017. [15] R. Mian, M. Shintani, and M. Inoue, “Cycle-Accurate Evaluation of Software-Hardware Co-Design of Decimal Computation in RISC-V Ecosystem,” in Proceedings of the 32nd IEEE International System-on-Chip Conference (SOCC), pp. 412-417, 2019. [16] Á. Vázquez, E. Antelo, and P. Montuschi, “A New Family of High-Performance Parallel Decimal Multipliers,” in Proceedings of the 18th IEEE Symposium on Computer Arithmetic (ARITH '07), pp. 195–204, 2007. [17] IEEE 754-2008 Working Group Mail Archive, available at http://grouper.ieee.org/groups/754/email/msg00801.html, 2003, retrieved on June 20, 2021. [18] S. Emami, M. Dorrigiv, and G. Jaberipur, “Radix-10 Addition with Radix-1000 Encoding of Decimal Operands,” in Proceedings of the 16th CSI International Symposiums on Computer Architecture & Digital Systems, pp. 139–144, 2012. [19] Á. Vázquez, and E. Antelo, “Conditional Speculative Decimal Addition,” in Proceedings of the 7th Conference on Real Numbers and Computers, pp. 47–57, 2006. [20] Á. Vázquez, “High-Performance Decimal Floating-Point Units,” Ph.D. dissertation, Univ Santiago de Compostela, 2009. [21] M. Dorrigiv, and G. Jaberipur, “Conditional speculative mixed decimal/binary adders via binary-coded-chiliad encoding,” in Computers & Electrical Engineering, Vol. 50, pp. 39–53, 2016. [22] M. Dorrigiv, “The IEEE 754-2019 Compatibility of the Binary Coded Chiliad (BCC) Encoding,” in Proceedings of the 20th CSI International Symposiums on Computer Architecture & Digital Systems, in print, 2020. [23] M. Cowlishaw, “Densely packed decimal encoding,” in IEE Proceedings - Computers and Digital Techniques, Vol. 149, No. 3, pp. 102–104, 2002. [24] IEE/ISO/IEC 60559:2020, “ISO/IEC/IEEE International Standard - Floating-point arithmetic,” International Organization for Standardization, pp. 1–86, 2020. [25] J.M. Muller, N. Brisebarre, F. de Dinechin, C. Jeannerod, V. Lefèvre, G. Melquiond, N. Revol, D. Stehlé, and S. Torres, “Handbook of Floating-Point Arithmetic,” Birkhäuser, 2010. [26] C. Tsen, S. Gonzalez-Navarro, and M.J. Schulte, “Hardware Design of a Binary Integer Decimal-based Floating-Point Adder,” in Proceedings of the 25th IEEE International Conference on Computer Design, pp. 288–295, 2007. [27] J.D. Nicoud, “Iterative Arrays for Radix Conversion,” in IEEE Transactions on Computers, Vol. C-20, No. 12, pp. 1479–1489, 1971. [28] IBM Corporation, “The ‘telco’ benchmark,” available at http://speleotrove.com/decimal/telco.html, retrieved on September 27, 2020. | ||
|
آمار تعداد مشاهده مقاله: 509 تعداد دریافت فایل اصل مقاله: 406 |
||