پیوندهای مفید
آمار
| تعداد نشریات | 8 |
| تعداد شماره‌ها | 432 |
| تعداد مقالات | 5,614 |
| تعداد مشاهده مقاله | 7,361,359 |
| تعداد دریافت فایل اصل مقاله | 6,167,520 |
Analysis and Design of High Gain, and Low Power CMOS Distributed Amplifier Utilizing a Novel Gain-cell Based on Combining Inductively Peaking and Regulated Cascode Concepts | ||
| AUT Journal of Electrical Engineering | ||
| مقاله 5، دوره 45، شماره 1، تیر 2013، صفحه 35-50 اصل مقاله (1.61 M) | ||
| نوع مقاله: Research Article | ||
| شناسه دیجیتال (DOI): 10.22060/eej.2013.424 | ||
| نویسندگان | ||
| Z. Baharvand* ؛ A. Hakimi | ||
| چکیده | ||
| In this study an ultra-broad band, low-power, and high-gain CMOS Distributed Amplifier (CMOS-DA) utilizing a new gain-cell based on the inductively peaking cascaded structure is presented. It is created by cascading of inductively coupled common-source (CS) stage and Regulated Cascode Configuration (RGC). The proposed three-stage DA is simulated in 0.13 μm CMOS process. It achieves flat and high of 26.5 ± 0.4 dB over the frequencies range from DC up to 13 GHz 3-dB bandwidth, and it dissipates only 9.95 mW. The IIP3 is simulated and achieved -10 dBm at 6 GHz. Also, simulated input referred 1-dB compression point at 6 GHz achieves the value of -20 dBm. Both input and output matches are better than -11 dB. To obtain the low power and high gain requirements, the advantages of the bulk terminal are exploited in the proposed CMOS-DA. It adopts the method of forward body biasing in output MOS transistor to achieve higher transconductance and lower power consumption. Additionally, the Monte Carlo (MC) simulation is performed to take into account the risks associated with various input parameters which they receive little or no consideration in simulating of designs utilizing ideal components. MC simulation predicts an estimate of the good accuracy performance of the proposed design under various conditions. | ||
| کلیدواژه‌ها | ||
| CMOS distributed amplifier؛ high-gain؛ ultra-broad band؛ low power؛ Regulated Cascode Configuration | ||
| عنوان مقاله [English] | ||
| Analysis and Design of High Gain, and Low Power CMOS Distributed Amplifier Utilizing a Novel Gain-cell Based on Combining Inductively Peaking and Regulated Cascode Concepts | ||
| نویسندگان [English] | ||
| Z. Baharvand؛ A. Hakimi | ||
| چکیده [English] | ||
| In this study an ultra-broad band, low-power, and high-gain CMOS Distributed Amplifier (CMOS-DA) utilizing a new gain-cell based on the inductively peaking cascaded structure is presented. It is created by cascading of inductively coupled common-source (CS) stage and Regulated Cascode Configuration (RGC). The proposed three-stage DA is simulated in 0.13 μm CMOS process. It achieves flat and high of 26.5 ± 0.4 dB over the frequencies range from DC up to 13 GHz 3-dB bandwidth, and it dissipates only 9.95 mW. The IIP3 is simulated and achieved -10 dBm at 6 GHz. Also, simulated input referred 1-dB compression point at 6 GHz achieves the value of -20 dBm. Both input and output matches are better than -11 dB. To obtain the low power and high gain requirements, the advantages of the bulk terminal are exploited in the proposed CMOS-DA. It adopts the method of forward body biasing in output MOS transistor to achieve higher transconductance and lower power consumption. Additionally, the Monte Carlo (MC) simulation is performed to take into account the risks associated with various input parameters which they receive little or no consideration in simulating of designs utilizing ideal components. MC simulation predicts an estimate of the good accuracy performance of the proposed design under various conditions. | ||
| کلیدواژه‌ها [English] | ||
| CMOS distributed amplifier, high-gain, ultra-broad band, low power, Regulated Cascode Configuration | ||
| مراجع | ||
|
[1] A. Ghadiri and K. Moez, “A new loss-reduced distributed amplifier structure”, in Circuits and Systems, 2009. ISCAS 2009. IEEE International Symposium on, pp. 2029- 2032, 2009. [2] A. Arbabian and A. M. Niknejad, “Design of a CMOS Tapered Cascaded Multistage Distributed Amplifier”, Microwave Theory and Techniques, IEEE Transactions on, vol. 57, pp. 938- 947, 2009. [3] P. Chen, J.-C. Kao, P.-C. Huang, and H. Wang, “A novel distributed amplifier with high gain, low noise and high output power in 0.18-μm CMOS technology”, in Microwave Symposium Digest (MTT), 2011 IEEE MTT-S International, pp. 1- 4, 2011. [4] G. Xin and N. Cam, “Low-power-consumption and high-gain CMOS distributed amplifiers using cascade of inductively coupled common-source gain cells for UWB systems”, Microwave Theory and Techniques, IEEE Transactions on, vol. 54, pp. 3278- 3283, 2006. [5] J.-F. Chang and Y.-S. Lin, “A High-Performance Distributed Amplifier Using Multiple Noise Suppression Techniques”,Microwave and Wireless Components Letters, IEEE, vol. 21, pp. 495- 497, 2011. [6] L. Yo-Sheng, C. Jin-Fa, and L. Shey-Shi, “Analysis and Design of CMOS Distributed Amplifier Using Inductively Peaking Cascaded Gain Cell for UWB Systems”, Microwave Theory and Techniques, IEEE Transactions on, vol. 59, pp. 2513- 2524, 2011. [7] A. H. Farzamiyan and A. Hakimi, “Low-power CMOS distributed amplifier using new cascade gain cell for high and low gain modes”, Analog Integrated Circuits and Signal Processing, vol. 74, pp. 453- 460, 2013. [8] J.-C. Chien, T.-Y. Chen, and L.-H. Lu, “A 9.5-dB 50-GHz Matrix Distributed Amplifier in 0.18-/spl mu/m CMOS”, in VLSI Circuits, 2006. Digest of Technical Papers. 2006 Symposium on, pp. 146- 147, 2006. [9] J.-C. Chien and L.-H. Lu, “40-Gb/s high-gain distributed amplifiers with cascaded gain stages in 0.18-μm CMOS”, Solid-State Circuits, IEEE Journal of, vol. 42, pp. 2715- 2725, 2007. [10] A. Arbabian and A. M. Niknejad, “A broadband distributed amplifier with internal feedback providing 660GHz GBW in 90nm CMOS”, in Solid-State Circuits Conference. ISSCC 2008. Digest of Technical Papers. IEEE International, 2008, pp. 196- 606, 2008. [11] D. Hua, Z. Shun'an, C. Yueyang, and Z. Qian, “A 25-GHz 9-dB distributed amplifier in CMOS technology”, in Electric Information and Control Engineering (ICEICE), 2011 International Conference on, pp. 12- 15, 2011. [12] T. H. Lee, The design of CMOS radio-frequency integrated circuits: Cambridge university press, 2004. [13] D. M. Pozar, “Microwave engineering, 3rd”, Danvers, MA: Wiley, 2005. [14] K. Entesari, A. R. Tavakoli, and A. Helmy, “CMOS Distributed Amplifiers With Extended Flat Bandwidth and Improved Input Matching Using Gate Line With Coupled Inductors”,Microwave Theory and Techniques, IEEE Transactions on, vol. 57, pp. 2862- 2871, 2009. [15] P. Heydari, “Design and Analysis of a Performance-Optimized CMOS UWB Distributed LNA”, Solid-State Circuits, IEEE Journal of, vol. 42, pp. 1892- 1905, 2007. [16] B. Razavi, Design of analog CMOS integrated circuits: Tata McGraw-Hill Education, 2002. [17] B. Razavi, Fundamentals of microelectronics vol. 1: Wiley Hoboken, 2008. [18] K. Moez and M. Elmasry, “A New Loss Compensation Technique for CMOS Distributed Amplifiers”, Circuits and Systems II: Express Briefs, IEEE Transactions on, vol. 56, pp. 185- 189, 2009. [19] D. A. Neamen, “Semiconductor physics and devices”, 1992, 1994. [20] M. Zakerhaghighi and A. Hakimi, “A Novel Topology of Variable Gain Distributed Amplifier in 0.13 μm CMOS Technology for UWB Applications”, Electronic Components and Materials, vol. 44, pp. 75- 83, 2014. [21] J.-F. Chang and Y.-S. Lin, “DC∼ 10.5 GHz complimentary metal oxide semiconductor distributed amplifier with RC gate terminal network for ultra-wideband pulse radio systems”, IET microwaves, antennas & propagation, vol. 6, pp. 127- 134, 2012. [22] D. Barras, F. Ellinger, H. Jackel, and W. Hirt, “A low supply voltage SiGe LNA for ultra-wideband frontends”, Microwave and Wireless Components Letters, IEEE, vol. 14, pp. 469- 471, 2004. [23] H. Chih-Yin, S. Tzu-Yu, and S. S. H. Hsu, “CMOS Distributed Amplifiers Using Gate–Drain Transformer Feedback Technique”, Microwave Theory and Techniques, IEEE Transactions on, vol. 61, pp. 2901- 2910, 2013. [24] V. Venkatraman and W. Burleson, “Impact of process variations on multi-level signaling for on-chip interconnects”, in VLSI Design, 2005. 18th International Conference on, pp. 362- 367, 2005. [25] S. Raychaudhuri, “Introduction to monte carlo simulation”, in Simulation Conference WSC 2008. Winter, 2008, pp. 91- 100, 2008. | ||
|
آمار تعداد مشاهده مقاله: 1,523 تعداد دریافت فایل اصل مقاله: 2,406 |
||