آمار

تعداد نشریات8
تعداد شماره‌ها422
تعداد مقالات5,535
تعداد مشاهده مقاله6,413,844
تعداد دریافت فایل اصل مقاله5,508,836
Yousefi, Mousa, Moradi, Zainab, Monfaredi, Khalil. (1401). CNTFET Based Pseudo Ternary Adder Design and Simulation. نشریه مهندسی عمران امیرکبیر, 54(Issue 2 (Special Issue)), 361-376. doi: 10.22060/eej.2022.20853.5443
Mousa Yousefi; Zainab Moradi; Khalil Monfaredi. "CNTFET Based Pseudo Ternary Adder Design and Simulation". نشریه مهندسی عمران امیرکبیر, 54, Issue 2 (Special Issue), 1401, 361-376. doi: 10.22060/eej.2022.20853.5443
Yousefi, Mousa, Moradi, Zainab, Monfaredi, Khalil. (1401). 'CNTFET Based Pseudo Ternary Adder Design and Simulation', نشریه مهندسی عمران امیرکبیر, 54(Issue 2 (Special Issue)), pp. 361-376. doi: 10.22060/eej.2022.20853.5443
Yousefi, Mousa, Moradi, Zainab, Monfaredi, Khalil. CNTFET Based Pseudo Ternary Adder Design and Simulation. نشریه مهندسی عمران امیرکبیر, 1401; 54(Issue 2 (Special Issue)): 361-376. doi: 10.22060/eej.2022.20853.5443

CNTFET Based Pseudo Ternary Adder Design and Simulation

AUT Journal of Electrical Engineering
مقاله 4، دوره 54، Issue 2 (Special Issue)، اسفند 2022، صفحه 361-376    اصل مقاله (1.13 M)
نوع مقاله: Research Article
شناسه دیجیتال (DOI): 10.22060/eej.2022.20853.5443
نویسندگان
Mousa Yousefi* ؛ Zainab Moradi؛ Khalil Monfaredi
Department of Electrical Engineering, Faculty of Engineering, Azarbaijan Shahid Madani University, Tabriz, Iran
چکیده
Utilizing multiple logic instead of binary logic levels makes the same system to be realized with reduced number of internal connections and wiring, and occupying smaller chip area while achieving higher operational speed. In spite of all the mentioned advantages, the multilevel logic systems relay on voltage dividing mechanism to provide suitable mid-voltage outputs. However, this requires a direct current flow from supply voltage to the ground, making the structure power hungry. Eliminating the mid-voltage outputs can help the structure to resemble binary design approach and be more power efficient, as will be discussed. In this paper, pseudo ternary addition blocks, namely a Half-Adder, a Full-Adder block are designed and implemented based on CNTFET, which try to eliminate 1 output for mid-stages wherever possible. The proposed adders are implemented, simulated and verified in HSPICE software using 32nm CNTFET technology. The simulation results reveal the proposed pseudo ternary Full-Adder block consumes just 1.037 mW power and has the propagation delay of 290 ps.
کلیدواژه‌ها
Carbone Nano tubes field effect transistor؛ pseudo ternary؛ Half-Adder؛ Full-Adder
مراجع
  1. K. Teo, R. Lacerda, M. Yang, A. Teh, L. Robinson, S. Dalal, et al., "Carbon Nanotube technology for solid state and vacuum electronics," IEE Proceedings-Circuits, Devices and Systems, vol. 151, pp. 443-451, 2004.
  2. Y. B. Kim, Y.-B. Kim, and F. Lombardi, "A novel design methodology to optimize the speed and power of the CNTFET circuits," in 2009 52nd IEEE International Midwest Symposium on Circuits and Systems, 2009, pp. 1130-1133.
  3. C. Wu, Y. Li, and S. Chai, "Design and simulation of a torus structure and route algorithm for network on chip," in 2007 7th International Conference on ASIC, 2007, pp. 1289-1292.
  4. S. A. Hosseini and S. Etezadi, "A novel very low-complexity multi-valued logic comparator in nanoelectronics," Circuits, Systems, and Signal Processing, vol. 39, pp. 223-244, 2020.
  5. B. S. Raghavan and V. K. Bhaaskaran, "Design of novel Multiple Valued Logic (MVL) circuits," in 2017 International Conference on Nextgen Electronic Technologies: Silicon to Software (ICNETS2), 2017, pp. 371-378.
  6. M. H. Moaiyeri, R. F. Mirzaee, A. Doostaregan, K. Navi, and O. Hashemipour, "A universal method for designing low-power Carbon Nanotube FET-based multiple-valued logic circuits," IET Computers & Digital Techniques, vol. 7, pp. 167-181, 2013.
  7. K. Sridharan, S. Gurindagunta, and V. Pudi, "Efficient multiternary digit adder design in CNTFET technology," IEEE transactions on Nanotechnology, vol. 12, pp. 283-287, 2013.
  8. 8. Sharifi, M. H. Moaiyeri, K. Navi, and N. Bagherzadeh, "Quaternary full adder cells based on Carbon Nanotube FETs," Journal of Computational Electronics, vol. 14, pp. 762-772, 2015.
  9. 9. P. KS and K. Gurumurthy, "Quaternary CMOS combinational logic circuits," in 2009 International Conference on Information and Multimedia Technology, 2009, pp. 538-542.
  10. A. D. Zarandi, M. R. Reshadinezhad, and A. Rubio, "A Systematic Method to Design Efficient Ternary High Performance CNTFET-Based Logic Cells," IEEE Access, vol. 8, pp. 58585-58593, 2020.
  11. M. Shahangian, S. A. Hosseini, and R. F. Mirzaee, "A Universal Method for Designing Multi-Digit Ternary to Binary Converter Using CNTFET," Journal of Circuits, Systems and Computers, p. 2050196, 2020.
  12. M. H. Moaiyeri, R. F. Mirzaee, K. Navi, and O. Hashemipour, "Efficient CNTFET-based ternary full adder cells for nanoelectronics," Nano-Micro Letters, vol. 3, pp. 43-50, 2011.
  13. J. Appenzeller, Y.-M. Lin, J. Knoch, Z. Chen, and P. Avouris, "Comparing Carbon Nanotube transistors-the ideal choice: a novel tunneling device design," IEEE Transactions on Electron Devices, vol. 52, pp. 2568-2576, 2005.
  14. Zahoor, Furqan, et al. "Ternary Arithmetic Logic Unit Design Utilizing Carbon Nanotube Field Effect Transistor (CNTFET) and Resistive Random Access Memory (RRAM)." Micromachines vol.12, No.11, pp. 1288, 2021.
  15. Moaiyeri, Mohammad Hossein, Molood Nasiri, and Nooshin Khastoo. "An efficient ternary serial adder based on Carbon Nanotube FETs." Engineering Science and Technology, an International Journal vol. 19, pp. 271-278, 2016.
.16 نیری, و نیری. "طراحی و شبیه سازی مدار جمع کننده پنج ارزشی جدید مبتنی بر ترانزیستور نانو نوار گرافن." مدل سازی در مهندسی 18.63 (2021).‎

  1. 17. Lin, Y.-B. Kim, and F. Lombardi, "A novel CNTFET-based ternary logic gate design," in 2009 52nd IEEE International Midwest Symposium on Circuits and Systems, 2009, pp. 435-438.
  2. M. Haselman and S. Hauck, "The future of integrated circuits: A survey of nanoelectronics," Proceedings of the IEEE, vol. 98, pp. 11-38, 2009.
19.J. Deng and H.-S. P. Wong, "A compact SPICE model for carbon-nanotube field-effect transistors including nonidealities and its application—Part II: Full device model and circuit performance benchmarking," IEEE Transactions on Electron Devices, vol. 54, pp. 3195-3205, 2007.

20.J. Deng and H.-S. P. Wong, "A compact SPICE model for carbon-nanotube field-effect transistors including nonidealities and its application—Part I: Model of the intrinsic channel region," IEEE Transactions on Electron Devices, vol. 54, pp. 3186-3194, 2007.

21.T. Sharma and L. Kumre, "CNTFET-based design of ternary arithmetic modules," Circuits, Systems, and Signal Processing, vol. 38, pp. 4640-4666, 2019.

22.P. Keshavarzian and K. Navi, "Universal ternary logic circuit design through Carbon Nanotube technology," International Journal of Nanotechnology, vol. 6, pp. 942-953, 2009.

23.M. H. Moaiyeri, A. Doostaregan, and K. Navi, "Design of energy-efficient and robust ternary circuits for nanotechnology," IET Circuits, Devices & Systems, vol. 5, pp. 285-296, 2011.

آمار
تعداد مشاهده مقاله: 489
تعداد دریافت فایل اصل مقاله: 442


سامانه مدیریت نشریات علمی. طراحی و پیاده سازی از سیناوب