پیوندهای مفید
آمار
| تعداد نشریات | 8 |
| تعداد شماره‌ها | 414 |
| تعداد مقالات | 5,478 |
| تعداد مشاهده مقاله | 6,010,523 |
| تعداد دریافت فایل اصل مقاله | 5,299,927 |
Hardware Trojan vulnerability assessment in digital integrated circuits using learnable classifiers | ||
| AUT Journal of Electrical Engineering | ||
| دوره 56، شماره 3، 2024، صفحه 419-438 اصل مقاله (1.31 M) | ||
| نوع مقاله: Research Article | ||
| شناسه دیجیتال (DOI): 10.22060/eej.2024.22910.5572 | ||
| نویسندگان | ||
| Hadi Jahanirad* ؛ Mohammad Fathi | ||
| Department of Electronics and Communication Engineering, University of Kurdistan, Sanandaj, Kurdistan, Iran | ||
| چکیده | ||
| Abstract- In the current distributed integrated circuits (IC) industry, the possibility of adversarial hardware attacks cannot be ignored. Hardware Trojans (HT) attacks may lead to information leakage or failure in security-critical systems. The wide range of HT types and related insertion strategies makes the HT detection process very complex. Consequently, developing IC design methodologies that are robust against HT insertion would be of great merit. To measure the HT robustness, a vulnerability analysis of the proposed circuits should be performed which involves several interrelated factors (e.g. the layout of white spaces distribution, the unutilized routing resources, the activity of the circuit nodes, the delay values of circuit paths, etc.). In this paper, a novel framework is proposed to classify the IC vulnerability level. First, a comprehensive dataset is generated considering different HTs insertion into the ISCAS 85 and ISCAS 89 benchmark circuits. Then extraction of efficient features from the input image is accomplished by pre-trained deep neural networks. Finally, the vulnerability level (which is defined as low vulnerable, moderately vulnerable, and highly vulnerable) of every circuit is extracted using various trained classifiers (Ensemble, SVM, Naïve Bayes, and KNN). Simulation results confirm a 25% improvement in classification accuracy in the most successful classifier (97%) compared with the most successful previous study (72%). | ||
| کلیدواژه‌ها | ||
| Ensemble Learning؛ Learnable Classifiers؛ Deep Neural Networks؛ Digital Circuits؛ Vulnerability Analysis؛ Hardware Trojans | ||
| مراجع | ||
|
[1] Hassan, R., Meng, X., Basu, K. and Dinakarrao, S.M.P., 2023. Circuit Topology-aware Vaccination-based Hardware Trojan Detection. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Jan 6 (2023).
[2] Moein, S., Gulliver, T. A., Gebali, F., & Alkandari, A. (2016). A new characterization of hardware trojans. IEEE Access, 4, 2721-2731.
[3] Tehranipoor, M., Salmani, H., Zhang, X., Wang, M., Karri, R., Rajendran, J., & Rosenfeld, K. (2010). Trustworthy hardware: Trojan detection and design-for-trust challenges. Computer, 44(7), 66-74.
[4] Hasegawa, K., Seira H., Kohei N., Shinsaku K., and Nozomu T.. "R-HTDetector: Robust hardware-Trojan detection based on adversarial training." IEEE Transactions on Computers 72, no. 2 (2023): 333-345.
[5] Chen, K., Arias, O., Guo, X., Deng, Q. and Jin, Y., 2022. IP-Tag: Tag-Based Runtime 3PIP Hardware Trojan Detection in SoC Platforms. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 42(1), pp.68-81.
[6] Cruz, J., Gaikwad, P., Nair, A., Chakraborty, P. and Bhunia, S., 2022, December. A Machine Learning Based Automatic Hardware Trojan Attack Space Exploration and Benchmarking Framework. In 2022 Asian Hardware Oriented Security and Trust Symposium (AsianHOST) (pp. 1-6). IEEE, Dec. 2022.
[7] Vaziri, M., Rahimifar, M.M. and Jahanirad, H., Robustness Scan of Digital Circuits Using Convolutional Neural Networks. In 2022 12th International Conference on Computer and Knowledge Engineering (ICCKE) (pp. 013-018). IEEE, Nov. 2022.
[8] Salmani, H., & Tehranipoor, M. M. (2016). Vulnerability analysis of a circuit layout to hardware Trojan insertion. IEEE Transactions on Information Forensics and Security, 11(6), 1214-1225.
[9] Bazzazi, A., Shalmani, M. T. M., & Hemmatyar, A. M. A. (2017). Hardware Trojan detection based on logical testing. Journal of Electronic Testing, 33(4), 381-395.
[10] Nowroz, A. N., Hu, K., Koushanfar, F., & Reda, S. (2014). Novel techniques for high-sensitivity hardware Trojan detection using thermal and power maps. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 33(12), 1792-1805.
[11] Kulkarni, A., Pino, Y., & Mohsenin, T. (2016, May). Adaptive real-time Trojan detection framework through machine learning. In 2016 IEEE International Symposium on Hardware Oriented Security and Trust (HOST) (pp. 120-123). IEEE.
[12] Guazzelli, R. A., Trindade, M. G., Guimarães, L. A., de Paiva Leite, T. F., Fesquet, L., & Bastos, R. P. (2020). Trojan Detection Test for Clockless Circuits. Journal of Electronic Testing, 1-9.
[13] Kulkarni, A., Pino, Y., & Mohsenin, T. (2016, March). SVM-based real-time hardware Trojan detection for many-core platform. In 2016 17th International Symposium on Quality Electronic Design (ISQED) (pp. 362-367). IEEE.
[14] Liakos, K. G., Georgakilas, G. K., Moustakidis, S., Karlsson, P., & Plessas, F. C. (2019, November). Machine Learning for Hardware Trojan Detection: A Review. In 2019 Panhellenic Conference on Electronics & Telecommunications (PACET) (pp. 1-6). IEEE.
[15] Rahimifar, M. M., & Jahanirad, H. (2020, October). Employing Image Processing Techniques for Hardware Trojans Detection. In 2020 10th International Conference on Computer and Knowledge Engineering (ICCKE) (pp. 187-192). IEEE.
[16] Vishnupriya, R., Nirmala Devi, M. (2021). Hardware Trojan Detection Using Deep Learning-Deep Stacked Auto Encoder. In: Gunjan, V.K., Zurada, J.M. (eds) Proceedings of International Conference on Recent Trends in Machine Learning, IoT, Smart Cities and Applications. Advances in Intelligent Systems and Computing, vol 1245. Springer, Singapore.
[17] Reshma, K., Priyatharishini, M., Nirmala Devi, M. (2019). Hardware Trojan Detection Using Deep Learning Technique. In: Wang, J., Reddy, G., Prasad, V., Reddy, V. (eds) Soft Computing and Signal Processing . Advances in Intelligent Systems and Computing, vol 898. Springer, Singapore.
[18] Priyatharishini, M. and Devi, M.N., 2022. A deep learning based malicious module identification using stacked sparse autoencoder network for VLSI circuit reliability. Measurement, 194, p.111055.
[19] Tehranipoor, M., & Koushanfar, F. (2010). A survey of hardware trojan taxonomy and detection. IEEE design & test of computers, 27(1), 10-25.
[20] Hossein-Talaee, H. and Jahanian, A., 2017, July. Layout vulnerability reduction against trojan insertion using security-aware white space distribution. In 2017 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) (pp. 551-555). IEEE.
[21] Trippel, Timothy, Kang G. Shin, Kevin B. Bush, and Matthew Hicks. "ICAS: an extensible framework for estimating the susceptibility of ic layouts to additive trojans." In 2020 IEEE Symposium on Security and Privacy (SP), pp. 1742-1759. IEEE, 2020.
[22] Bhunia, S., Hsiao, M. S., Banga, M., & Narasimhan, S. (2014). Hardware Trojan attacks: Threat analysis and countermeasures. Proceedings of the IEEE, 102(8), 1229-1247.
[23] Hicks, Matthew, Murph Finnicum, Samuel T. King, Milo MK Martin, and Jonathan M. Smith. "Overcoming an untrusted computing base: Detecting and removing malicious hardware automatically." In 2010 IEEE symposium on security and privacy, pp. 159-172. IEEE, 2010.
[24] Waksman, Adam, Matthew Suozzo, and Simha Sethumadhavan. "FANCI: identification of stealthy malicious logic using boolean functional analysis." In Proceedings of the 2013 ACM SIGSAC conference on Computer & communications security, pp. 697-708. 2013.
[25] Sullivan, Dean, Jeff Biggers, Guidong Zhu, Shaojie Zhang, and Yier Jin. "FIGHT-metric: Functional identification of gate-level hardware trustworthiness." In Proceedings of the 51st Annual Design Automation Conference, pp. 1-4. 2014.
[26] Yao, Song, Xiaoming Chen, Jie Zhang, Qiaoyi Liu, Jia Wang, Qiang Xu, Yu Wang, and Huazhong Yang. "FASTrust: Feature analysis for third-party IP trust verification." In 2015 IEEE International Test Conference (ITC), pp. 1-10. IEEE, 2015.
[27] Chen, Xiaoming, Qiaoyi Liu, Song Yao, Jia Wang, Qiang Xu, Yu Wang, Yongpan Liu, and Huazhong Yang. "Hardware trojan detection in third-party digital intellectual property cores by multilevel feature analysis." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 37, no. 7 (2017): 1370-1383.
[28] Salmani, Hassan. "COTD: Reference-free hardware trojan detection and recovery based on controllability and observability in gate-level netlist." IEEE Transactions on Information Forensics and Security 12, no. 2 (2016): 338-350.
[29] Tebyanian, Mahshid, Azadeh Mokhtarpour, and Alireza Shafieinejad. "SC-COTD: Hardware Trojan Detection Based on Sequential/Combinational Testability Features using Ensemble Classifier." Journal of Electronic Testing 37, no. 4 (2021): 473-487.
[30] Kok, Chee Hoo, Chia Yee Ooi, Mehrdad Moghbel, Nordinah Ismail, Hau Sim Choo, and Michiko Inoue. "Classification of Trojan nets based on SCOAP values using supervised learning." In 2019 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1-5. IEEE, 2019.
[31] Kok, Chee Hoo, Chia Yee Ooi, Michiko Inoue, Mehrdad Moghbel, Sreedharan Baskara Dass, Hau Sim Choo, Nordinah Ismail, and Fawnizu Azmadi Hussin. "Net classification based on testability and netlist structural features for hardware trojan detection." In 2019 IEEE 28th Asian Test Symposium (ATS), pp. 105-1055. IEEE, 2019.
[32] Hasegawa, Kento, Masao Yanagisawa, and Nozomu Togawa. "Trojan-feature extraction at gate-level netlists and its application to hardware-Trojan detection using random forest classifier." In 2017 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1-4. IEEE, 2017.
[33] Hasegawa, Kento, Youhua Shi, and Nozomu Togawa. "Hardware trojan detection utilizing machine learning approaches." In 2018 17th IEEE International Conference On Trust, Security And Privacy In Computing And Communications/12th IEEE International Conference On Big Data Science And Engineering (TrustCom/BigDataSE), pp. 1891-1896. IEEE, 2018.
[34] Hasegawa, Kento, Masao Yanagisawa, and Nozomu Togawa. "Trojan-net classification for gate-level hardware design utilizing boundary net structures." IEICE TRANSACTIONS on Information and Systems 103, no. 7 (2020): 1618-1622.
[35] Abbassi, Imran Hafeez, Faiq Khalid, Osman Hasan, Awais Mehmood Kamboh, and Muhammad Shafique. "McSeVIC: A model checking based framework for security vulnerability analysis of integrated circuits." IEEE Access 6 (2018): 32240-32257.
[36] Khalid, Faiq, Imran Hafeez Abbassi, Semeen Rehman, Awais Mehmood Kamboh, Osman Hasan, and Muhammad Shafique. "ForASec: Formal Analysis of Hardware Trojan-Based Security Vulnerabilities in Sequential Circuits." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 41, no. 4 (2021): 1167-1180.
[37] Salmani, Hassan, and Mark M. Tehranipoor. "Vulnerability analysis of a circuit layout to hardware trojan insertion." IEEE Transactions on Information Forensics and Security 11, no. 6 (2016): 1214-1225.
[38] Bakhshizadeh, Mahmoud, and Ali Jahanian. "Trojan Vulnerability Map: an efficient metric for modeling and improving the security level of hardware." IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences 97, no. 11 (2014): 2218-2226.
[39] Ba, P. S., Dupuis, S., Palanichamy, M., Flottes, M. L., Di Natale, G., & Rouzeyre, B. (2016, July). Hardware trust through layout filling: A hardware Trojan prevention technique. In 2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) (pp. 254-259). IEEE.
[40] Najm, F. N. (1994). A survey of power estimation techniques in VLSI circuits. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2(4), 446-455.
[41] Nasser, Y., Lorandel, J., Prévotet, J. C., & Hélard, M. (2020). RTL to Transistor Level Power Modelling and Estimation Techniques for FPGA and ASIC: A Survey. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
[42] Murray, K. E., Petelin, O., Zhong, S., Wang, J. M., Eldafrawy, M., Legault, J. P., ... & Betz, V. (2020). Vtr 8: High-performance cad and customizable fpga architecture modelling. ACM Transactions on Reconfigurable Technology and Systems (TRETS), 13(2), 1-55.
[43] Acero, C., Feltham, D., Liu, Y., Moghaddam, E., Mukherjee, N., Patyra, M., ... & Zawada, J. (2017). Embedded deterministic test points. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 25(10), 2949-2961.
[44] Breiman, Leo. "Random forests." Machine learning 45 (2001): 5-32.
[45] Friedman, Jerome H. "Greedy function approximation: a gradient boosting machine." Annals of statistics (2001): 1189-1232.
[46] Chen, Tianqi, and Carlos Guestrin. "Xgboost: A scalable tree boosting system." In Proceedings of the 22nd acm sigkdd international conference on knowledge discovery and data mining, pp. 785-794. 2016.
[47] Savari, M. A., & Jahanirad, H. (2020). NN-SSTA: A deep neural network approach for statistical static timing analysis. Expert Systems with Applications, 149, 113309.
[48] P. Jamieson, K. B. Kent, F. Gharibian, and L. Shannon. 2010. Odin II - An open-source verilog hdl synthesis tool for CAD research. In Proceedings of the International Symposium on Field-Programmable Custom Computing Machines (FCCM’10). 149–156.
[49] Berkley Logic Synthesis and Verification Group. 2018. ABC: A System for Sequential Synthesis and Verification. Retrieved from http://www.eecs.berkeley.edu/∼alanmi/abc/.
[50] J. Lamoureux and S.J.E. Wilton, “Activity estimation for Field Programmable Gate Arrays”, Proc. Intl Conf. Field-Prog. Logic and Applications (FPL), 2006, pp. 87-94. | ||
|
آمار تعداد مشاهده مقاله: 470 تعداد دریافت فایل اصل مقاله: 207 |
||