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Design of a Fuzzy Controller Chip with New Structure, Supporting Rational-Powered Membership Functions | ||
| AUT Journal of Electrical Engineering | ||
| مقاله 8، دوره 41، شماره 2، بهمن 2009، صفحه 65-71 اصل مقاله (819.04 K) | ||
| نوع مقاله: Research Article | ||
| شناسه دیجیتال (DOI): 10.22060/eej.2009.286 | ||
| نویسندگان | ||
| A. Naderii* 1؛ H. Ghasemzadehii2؛ A. Pourazar2؛ M. Aliasgharyii2 | ||
| 1Corresponding Author, A. Naderi is with the Department of Electronic Engineering, urmia University, Urmia, Iran (e-mail: ali.n.1384@gmail.com). | ||
| 2H. Ghasemzadeh, A. Pourazar and M. Aliasghary are with the Department of Electronic Engineering, urmia University, Urmia, Iran (e-mail: hadi.g.1384@gamil.com, pourazar.alireza@gmail.com, m.aliasghari@gmail.com ). | ||
| چکیده | ||
| In this paper, a new structure possessing the advantages of low-power consumption, less hardware and high-speed is proposed for fuzzy controller. The maximum output delay for general fuzzy logic controllers (FLC) is about 86 ns corresponding to 11.63 MFLIPS (fuzzy logic inference per second) while this amount of the delay in the designed fuzzy controller becomes 52ns that corresponds to 19.23 MFLIPS. This mixed analog/digital realization of the circuit makes the design programmable and extendable. The proposed controller supports Rational-Power Membership Functions with a resolution of 0.03125. Simulation results of the controller using HSPICE simulator level 49 in 0.35um in CMOS process technology (BSIM3v3) show an average power consumption of 4.38mW, and an RMS error of 1.26%. This controller can be used in many applications in which there is a need for a controller chip by correct programming with system experts. Meanwhile the whole area of the chip is 0.0775mm2. | ||
| کلیدواژهها | ||
| Fuzzy controller؛ Rational-powered membership function؛ CMOS؛ low power | ||
| عنوان مقاله [English] | ||
| Design of a Fuzzy Controller Chip with New Structure, Supporting Rational-Powered Membership Functions | ||
| چکیده [English] | ||
| In this paper, a new structure possessing the advantages of low-power consumption, less hardware and high-speed is proposed for fuzzy controller. The maximum output delay for general fuzzy logic controllers (FLC) is about 86 ns corresponding to 11.63 MFLIPS (fuzzy logic inference per second) while this amount of the delay in the designed fuzzy controller becomes 52ns that corresponds to 19.23 MFLIPS. This mixed analog/digital realization of the circuit makes the design programmable and extendable. The proposed controller supports Rational-Power Membership Functions with a resolution of 0.03125. Simulation results of the controller using HSPICE simulator level 49 in 0.35um in CMOS process technology (BSIM3v3) show an average power consumption of 4.38mW, and an RMS error of 1.26%. This controller can be used in many applications in which there is a need for a controller chip by correct programming with system experts. Meanwhile the whole area of the chip is 0.0775mm2. | ||
| کلیدواژهها [English] | ||
| Fuzzy controller, Rational-powered membership function, CMOS, low power | ||
| مراجع | ||
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[1] M. Mottaghi Kashtiban, A. Khoei, and Kh. Hadidi; “Optimization of Rational-Powered Membership Functions Using Extended Kalman Filter,” Journal of Fuzzy Sets and Systems (FSS), Elsevier, 159(23), 2007. [2] C. Y.Chen, Y. T. Hsieh and B. D. Liu; “Circuit implementation of linguistic-hedge fuzzy logic cotroller in current-mode” IEEE Transaction on Fuzzy Systems, Vol. 11, pp.624-646, 2003. [3] M. Mottaghi Kashtiban, A. Khoei, and Kh. Hadidi; “A Current-mode, First-Order Takagi-Sugeno-Kang FLC, Supporting Rational-Powered Membership Functions” IEICE TRANS. ELECTRON., Vol. E90-C, No.6 2007. [4] R. Amirkhanzadeh, A. Khoei, Kh. Hadidi, “A mixed-signal current-mode fuzzy logic controller”, Int. Journal of Electronics and Communications, pp. 177-184, 2005. [5] C. Dualibe, P. Jespers, and M. Verleysen; “A 5.26 MFLIPS programmable Analogue Fuzzy Logic Controller in a Standard CMOS 2.4μ Technology”, ISCAS, pp. 377-380, May 2000. [6] Y.Chen, Y.Huang, D.Liu; “Current-mode defuzzifier circuit to realise the centroid strategy“, IEE Proc.-Circuits Devices Syst., vol. 144, No. 5, Octobr 1997. [7] A. Naderi, A. Khoei, Kh. Hadidi, "High resolution RPMF using logarithmic and exponential approximation in CMOS technology," 16th International Conf. on Electrical Engineering, (ICEE) Tehran, Iran, 248 – 254, 2008. [8] A. j. Lopez-martin and A. Carlosena; “Current-Mode Multiplier/Divider Circuits Based on the MOS Translinear Principle,” Analog Integrated Circuits and Signal Processing, pp. 265-278, 2001. [9] A. Naderi, A. Khoei, Kh. Hadidi; “A New High Speed and Low Power 4-Quadrant CMOS Analog Multiplier in Current-Mode”, International Journal of Electronics and Communications, Elsevier, Vol. 63, Issue 9, 2009. | ||
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