آمار

تعداد نشریات7
تعداد شماره‌ها399
تعداد مقالات5,389
تعداد مشاهده مقاله5,288,012
تعداد دریافت فایل اصل مقاله4,882,750
Yousefi, Mousa, Monfaredi, Khalil. (1402). Implementation of N-inputs Ternary to Binary Converter with Multipart division technique Based on CNTFET. نشریه مهندسی عمران امیرکبیر, 55(2), 255-280. doi: 10.22060/eej.2023.22072.5511
Mousa Yousefi; Khalil Monfaredi. "Implementation of N-inputs Ternary to Binary Converter with Multipart division technique Based on CNTFET". نشریه مهندسی عمران امیرکبیر, 55, 2, 1402, 255-280. doi: 10.22060/eej.2023.22072.5511
Yousefi, Mousa, Monfaredi, Khalil. (1402). 'Implementation of N-inputs Ternary to Binary Converter with Multipart division technique Based on CNTFET', نشریه مهندسی عمران امیرکبیر, 55(2), pp. 255-280. doi: 10.22060/eej.2023.22072.5511
Yousefi, Mousa, Monfaredi, Khalil. Implementation of N-inputs Ternary to Binary Converter with Multipart division technique Based on CNTFET. نشریه مهندسی عمران امیرکبیر, 1402; 55(2): 255-280. doi: 10.22060/eej.2023.22072.5511

Implementation of N-inputs Ternary to Binary Converter with Multipart division technique Based on CNTFET

AUT Journal of Electrical Engineering
مقاله 10، دوره 55، شماره 2، 2023، صفحه 255-280    اصل مقاله (1.49 M)
نوع مقاله: Research Article
شناسه دیجیتال (DOI): 10.22060/eej.2023.22072.5511
نویسندگان
Mousa Yousefi* ؛ Khalil Monfaredi
Department of Electrical Engineering, Faculty of Engineering, Azarbaijan Shahid Madani University, Tabriz, Iran
چکیده
In this paper, the new structure N×M (N-Ternary inputs and M-Binary outputs) Ternary to Binary Converter based on the Carbone Nanao Tube Field Effect Transistor is presented. The Carbone Nanao Tube Field Effect Transistor (CNTFET) has special properties such as controlled threshold voltage. The aforementioned advantages related to the multi-level (more specifically Ternary) circuits and systems based on CNTFET technology have encouraged researchers to put more effort into on their design and realization in recent years. The Encoder (one input- five outputs), 3×1 multiplexer (one input – one selector-three outputs), and special Adder blocks (Full Adder and Half Adder) are base blocks that are implemented by transistor level using special properties of CNTFET transistor. In general, to implement a N-input ternary-to-binary converter, the number of inputs can be divided into two small converters, and also a ternary-to-binary converter can be designed for each input. In this paper, 2×4, 3×5, 4×7 and 5×8 Ternary to Binary converters are designed and simulated by Hospice and 32 nanometer technology. The result of the simulation is shown that the 5×8 Ternary to Binary converter has 1.89 µW DC-Power and 52 ps propagation delay. The proposed 5×8 TTBC converter is implemented by 365 CNTFET transistors and divided into two ternary to binary converters.
کلیدواژه‌ها
CNTFET؛ Ternary؛ Binary- Multi-level- converter
مراجع
  1. Roy, K., S. Mukhopadhyay, and H. Mahmoodi-Meimand, Leakage current mechanisms and leakage reduction techniques in deep-submicrometer CMOS circuits. Proceedings of the IEEE, 2003. 91(2): p. 305-327.
  2. Navi, K., et al., Five-input majority gate, a new device for quantum-dot cellular automata. Journal of Computational and Theoretical Nanoscience, 2010. 7(8): p. 1546-1553.
  3. Teo, K., et al., Carbon nanotube technology for solid state and vacuum electronics. IEE Proceedings-Circuits, Devices and Systems, 2004. 151(5): p. 443-451.
  4. Sinha, S.K. and S. Chaudhury. Advantage of CNTFET characteristics over MOSFET to reduce leakage power. in 2014 2nd International Conference on Devices, Circuits and Systems (ICDCS). 2014. IEEE.
  5. Appenzeller, J., Carbon nanotubes for high-performance electronics—Progress and prospect. Proceedings of the IEEE, 2008. 96(2): p. 201-211.
  6. Appenzeller, J., et al., Comparing carbon nanotube transistors-the ideal choice: a novel tunneling device design. IEEE Transactions on Electron Devices, 2005. 52(12): p. 2568-2576.
  7. Haselman, M. and S. Hauck, The future of integrated circuits: A survey of nanoelectronics. Proceedings of the IEEE, 2009. 98(1): p. 11-38.
  8. Lin, Y.-M., et al., High-performance carbon nanotube field-effect transistor with tunable polarities. IEEE transactions on nanotechnology, 2005. 4(5): p. 481-489.
  9. Miller, D.M. and M.A. Thornton, Multiple valued logic: Concepts and representations. Synthesis lectures on digital circuits and systems, 2007. 2(1): p. 1-127.
  10. Moaiyeri, M.H., et al., A universal method for designing low-power carbon nanotube FET-based multiple-valued logic circuits. IET Computers & Digital Techniques, 2013. 7(4): p. 167-181.
  11. Raghavan, B.S. and V.K. Bhaaskaran. Design of novel Multiple Valued Logic (MVL) circuits. in 2017 International Conference on Nextgen Electronic Technologies: Silicon to Software (ICNETS2). 2017. IEEE.
  12. Abiri, E., A. Darabi, and S. Salem, Design of multiple-valued logic gates using gate-diffusion input for image processing applications. Computers & Electrical Engineering, 2018. 69: p. 142-157.
  13. Balla, P.C. and A. Antoniou, Low power dissipation MOS ternary logic family. IEEE Journal of Solid-State Circuits, 1984. 19(5): p. 739-749.
  14. Hosseini, S.A. and S. Etezadi, A novel very low-complexity multi-valued logic comparator in nanoelectronics. Circuits, Systems, and Signal Processing, 2020. 39(1): p. 223-244.
  15. Keshavarzian, P. and R. Sarikhani, A novel CNTFET-based ternary full adder. Circuits, Systems, and Signal Processing, 2014. 33(3): p. 665-679.
  16. KS, V.P. and K. Gurumurthy. Quaternary CMOS combinational logic circuits. in 2009 International Conference on Information and Multimedia Technology. 2009. IEEE.
  17. Lin, S., Y.-B. Kim, and F. Lombardi, CNTFET-based design of ternary logic gates and arithmetic circuits. IEEE transactions on nanotechnology, 2009. 10(2): p. 217-225.
  18. Lin, S., Y.-B. Kim, and F. Lombardi. A novel CNTFET-based ternary logic gate design. in 2009 52nd IEEE International Midwest Symposium on Circuits and Systems. 2009. IEEE.
  19. Moaiyeri, M.H., A. Doostaregan, and K. Navi, Design of energy-efficient and robust ternary circuits for nanotechnology. IET Circuits, Devices & Systems, 2011. 5(4): p. 285-296.
  20. Murotiya, S.L., A. Gupta, and S. Vasishth. CNTFET-based design of dynamic ternary full adder cell. in 2014 Annual IEEE India Conference (INDICON). 2014. IEEE.
  21. Rahbari, K. and S.A. Hosseini, Novel ternary D-Flip-Flap-Flop and counter based on successor and predecessor in nanotechnology. AEU-International Journal of Electronics and Communications, 2019. 109: p. 107-120.
  22. Roosta, E. and S.A. Hosseini, A novel multiplexer-based quaternary full adder in nanoelectronics. Circuits, Systems, and Signal Processing, 2019. 38(9): p. 4056-4078.
  23. Zarandi, A.D., M.R. Reshadinezhad, and A. Rubio, A Systematic Method to Design Efficient Ternary High Performance CNTFET-Based Logic Cells. IEEE Access, 2020. 8: p. 58585-58593.
  24. Shahangian, M., S.A. Hosseini, and R.F. Mirzaee, A Universal Method for Designing Multi-Digit Ternary to Binary Converter Using CNTFET. Journal of Circuits, Systems and Computers, 2020. 29(12): p. 2050196.
  25. Wei, L., et al., Noniterative compact modeling for intrinsic carbon-nanotube FETs: Quantum capacitance and ballistic transport. IEEE transactions on electron devices, 2011. 58(8): p. 2456-2465.
  26. Charlier, J.-C. and P. Lambin, Electronic structure of carbon nanotubes with chiral symmetry. Physical Review B, 1998. 57(24): p. R15037.
  27. Avouris, P. and R. Martel, Progress in carbon nanotube electronics and photonics. MRS bulletin, 2010. 35(4): p. 306-313.
آمار
تعداد مشاهده مقاله: 237
تعداد دریافت فایل اصل مقاله: 187


سامانه مدیریت نشریات علمی. طراحی و پیاده سازی از سیناوب