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Design and Simulation of a Modified 32-bit ROM-based Direct Digital Frequency Synthesizer on FPGA | ||
| AUT Journal of Electrical Engineering | ||
| مقاله 4، دوره 47، شماره 1، تیر 2015، صفحه 23-29 اصل مقاله (611.03 K) | ||
| نوع مقاله: Research Article | ||
| شناسه دیجیتال (DOI): 10.22060/eej.2015.518 | ||
| نویسندگان | ||
| P. Soleimani Abhari1؛ M. Dosaranian Moghadam* 2 | ||
| 1MSc. Student, Department of Electrical, Biomedical and Mechatronics Engineering, Qazvin Branch, Islamic Azad University, Qazvin, Iran | ||
| 2Assistant Professor, Department of Electrical, Biomedical and Mechatronics Engineering, Qazvin Branch, Islamic Azad University, Qazvin, Iran | ||
| چکیده | ||
| This paper presents a modified 32-bit ROM-based Direct Digital Frequency Synthesizer (DDFS). Maximum output frequency of the DDFS is limited by the structure of the accumulator used in the DDFS architecture. The hierarchical pipeline accumulator (HPA) presented in this paper has less propagation delay time rather than the conventional structures. Therefore, it results in both higher maximum operating frequency and higher maximum output frequency. Ripple Carry Adder (RCA) is used at each stage of Conventional pipeline accumulators, whereas the modified pipeline technique contains Carry Look-ahead Adder (CLA) instead of RCA. The proposed method consists of hierarchical adders that have three parts, two blocks of 4-bit CLA and a separated block to estimate carry bits independently. To reach a better frequency resolution in the DDFS, larger phase accumulator is needed. Moreover, in conventional DDFSs, as the number of phase bits increases, to have non-truncated phase mapping, huge amount of memory will be needed. The trigonometric relations of the sine and the cosine functions are used in the phase mapping technique proposed by Symon in order to reduce the size of the Look Up Table (LUT). The method applied in this work combines quarter wave symmetry of the sine samples, the phase difference between the sine and the cosine samples and trigonometric relations of the sine and the cosine functions to reduce the total memory size. The SFDR of the output wave will remain approximately constant (132 dBc) in comparison with the previous works. Finally, the proposed architecture is simulated on Stratix II FPGA. This structure has the frequency range of 0 to 245 MHz with 0.05 Hertz frequency resolution. | ||
| کلیدواژه‌ها | ||
| DDFS؛ SFDR؛ Trigonometric identities؛ Phase mapping technique؛ Pipeline Accumulator | ||
| عنوان مقاله [English] | ||
| Design and Simulation of a Modified 32-bit ROM-based Direct Digital Frequency Synthesizer on FPGA | ||
| نویسندگان [English] | ||
| P. Soleimani Abhari1؛ M. Dosaranian Moghadam2 | ||
| 1MSc. Student, Department of Electrical, Biomedical and Mechatronics Engineering, Qazvin Branch, Islamic Azad University, Qazvin, Iran | ||
| 2Assistant Professor, Department of Electrical, Biomedical and Mechatronics Engineering, Qazvin Branch, Islamic Azad University, Qazvin, Iran | ||
| چکیده [English] | ||
| This paper presents a modified 32-bit ROM-based Direct Digital Frequency Synthesizer (DDFS). Maximum output frequency of the DDFS is limited by the structure of the accumulator used in the DDFS architecture. The hierarchical pipeline accumulator (HPA) presented in this paper has less propagation delay time rather than the conventional structures. Therefore, it results in both higher maximum operating frequency and higher maximum output frequency. Ripple Carry Adder (RCA) is used at each stage of Conventional pipeline accumulators, whereas the modified pipeline technique contains Carry Look-ahead Adder (CLA) instead of RCA. The proposed method consists of hierarchical adders that have three parts, two blocks of 4-bit CLA and a separated block to estimate carry bits independently. To reach a better frequency resolution in the DDFS, larger phase accumulator is needed. Moreover, in conventional DDFSs, as the number of phase bits increases, to have non-truncated phase mapping, huge amount of memory will be needed. The trigonometric relations of the sine and the cosine functions are used in the phase mapping technique proposed by Symon in order to reduce the size of the Look Up Table (LUT). The method applied in this work combines quarter wave symmetry of the sine samples, the phase difference between the sine and the cosine samples and trigonometric relations of the sine and the cosine functions to reduce the total memory size. The SFDR of the output wave will remain approximately constant (132 dBc) in comparison with the previous works. Finally, the proposed architecture is simulated on Stratix II FPGA. This structure has the frequency range of 0 to 245 MHz with 0.05 Hertz frequency resolution. | ||
| کلیدواژه‌ها [English] | ||
| DDFS, SFDR, Trigonometric identities, Phase mapping technique, Pipeline Accumulator | ||
| مراجع | ||
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[1] Ibrahim, S. H., Ali, S. H. M., and Islam, M. S., “Design A 24-Bits Pipeline Phase Accumulator For Direct Digital Frequency Synthesizer”, IEEE 2012 international symposium on instrumentation and measurement sensor network and automation (IMSNA), pp. 393-397, 2012. [2] Ibrahim, S. H., Ali, S. H. M., and Islam, M. S., “12-Bit High Speed Direct Digital Frequency Synthesizer Based on Pipelining Phase Accumulator Design”, Journal of Asian Scientific Research, vol. 2, no.11, pp. 667-672, 2011. [3] Chappell, M. and McEwan, A., “A Low Power High Speed Accumulator for DDFS Applications”, IEEE Proceedings of the 2004 International Symposium on Circuits and Systems, vol.2, pp. 797-800, May 2004. [4] Vankka, J., “Direct Digital Synthesizers: Theory, Design and Applications”, Helsinki University of Technology Department of Electrical and Communications Engineering Electronic Circuit Design Laboratory, PHD thesis, November 2000. [5] Alkurwy, S. H., Md Ali, S. H., and Shabiul Islam, Md., “Implementation of Low Power Compressed ROM for Direct Digital Frequency Synthesizer”, IEEE international conference on system science and engineering (ICSSE), pp. 309-312, 2014. [6] Wang, G., “An FPGA-based Spur-Reduced Numerically Controlled Oscillator”, IEEE international conference on system science and engineering (ICSSE), pp. 187-192, 2012. [7] Ko, Lu-Ting, Chen, Jwu-E., Shieh, Yaw-Shih, Hsin, Hsi-Chin, and Sung, Tze-Yun, “Difference Equation-Based Digital Frequency Synthesizer”, Mathematical Problems in Engineering, Hindawi, vol. 2012, pp. 1-12, 2012. [8] Symons, P.R., “DDFS Phase Mapping Technique”, IET, Electronics Letters, vol. 38, no. 21, pp.1291-1292, 2002. [9] Cardarilli, G.C., D’Alessio, M., Di Nunzio, L., Fazzolari, R., Murgia, D., and Re, M., “FPGA implementation of a low-area/high-SFDR DDFS architecture”, 10th International Symposium on Signals, Circuits and Systems (ISSCS), pp. 1-4, July 2011. [10] Compton, K., “Carry Lookahead Adders”, Logic and Computer Design Fundamentals (4th Edition), UW-Madison, 2010, http://www.ece.uvic.ca. | ||
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