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Two-step Dynamic Foreground Auto-Calibration of Binary Weighted Current Steering DAC | ||
| AUT Journal of Electrical Engineering | ||
| مقاله 3، دوره 57، شماره 3، 2025، صفحه 445-460 اصل مقاله (880.98 K) | ||
| نوع مقاله: Research Article | ||
| شناسه دیجیتال (DOI): 10.22060/eej.2025.23723.5629 | ||
| نویسندگان | ||
| Sara Jan Mohammadi؛ Khalil Monfaredi* ؛ Mousa Yousefi | ||
| Department of Electrical and Electronic Engineering, Faculty of Engineering, Azarbaijan Shahid Madani University, Tabriz, Iran | ||
| چکیده | ||
| This paper presents a novel and versatile calibration technique designed for application in Binary Weighted Current Steering Digital-to-Analog Converters (DACs). The primary motivation for this work stems from the limited availability of calibration methods that address matching accuracy, despite the widespread adoption of such converters. The proposed technique facilitates automatic calibration of the DAC as required, leveraging two distinct clock signals: a low-frequency clock for calibration and a high-frequency clock for standard operational modes. The calibration process employs a unique and algorithmically-driven calibration block to systematically eliminate transistor mismatch-induced current errors across all current sources. A configurable triple-path scheme is implemented to steer previously calibrated least significant bit (LSB) currents into the summing node, which subsequently updates the reference current. This updated reference is then used to calibrate the next most significant bit (MSB) current. To validate the effectiveness of the proposed technique, simulations were conducted for a 10-bit DAC using Cadence tools with TSMC 180nm CMOS technology. The DAC was subjected to an intentionally introduced current error of up to 125 LSB in the binary-weighted current blocks. The simulation, performed at a sampling frequency of 125 MHz with a 1.8 V supply voltage and a 500 nA LSB current, demonstrated the robustness and accuracy of the proposed calibration method. | ||
| کلیدواژهها | ||
| Binary Weighted؛ Current Steering DAC؛ Two-Step Coarse/Fine Calibration؛ Dynamic Foreground Calibration؛ Voltage Comparison | ||
| مراجع | ||
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[1] S. Sarkar, S. Banerjee, An 8-bit low power DAC with re-used distributed binary cells architecture for reconfigurable transmitters, Microelectronics Journal, 45(6) (2014) 666-677.
[2] J. Deveugele, M.S. Steyaert, A 10-bit 250-MS/s binary-weighted current-steering DAC, IEEE Journal of Solid-State Circuits, 41(2) (2006) 320-329.
[3] W.-T. Lin, T.-H. Kuo, A compact dynamic-performance-improved current-steering DAC with random rotation-based binary-weighted selection, IEEE Journal of Solid-State Circuits, 47(2) (2012) 444-453.
[4] S.-C. Yi, An 8-bit current-steering digital to analog converter, AEU-International Journal of Electronics and Communications, 66(5) (2012) 433-437.
[5] X. Wu, P. Palmers, M.S. Steyaert, A 130 nm CMOS 6-bit full Nyquist 3 GS/s DAC, IEEE Journal of Solid-State Circuits, 43(11) (2008) 2396-2403.
[6] S.N. Mohyar, M. Murakami, A. Motozawa, H. Kobayashi, O. Kobayashi, T. Matsuura, SFDR Improvement Algorithms for Current-Steering DACs, Key Engineering Materials, 643 (2015) 101.
[7] F.-T. Chou, C.-C. Hung, Glitch energy reduction and SFDR enhancement techniques for low-power binary-weighted current-steering DAC, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 24(6) (2016) 2407-2411.
[8] S.-C. Yi, A 10-bit current-steering CMOS digital to analog converter, AEU-International Journal of Electronics and Communications, 69(1) (2015) 14-17.
[9] G. Guo, Y. Wang, W. Su, S. Jia, G. Zhang, X. Zhang, Binary tree structure random Dynamic Element Matching technique in current-steering DACs, in: Solid-State and Integrated Circuit Technology (ICSICT), 2012 IEEE 11th International Conference on, IEEE, 2012, pp. 1-3.
[10] M.-H. Shen, J.-H. Tsai, P.-C. Huang, Random swapping dynamic element matching technique for glitch energy minimization in current-steering DAC, IEEE Transactions on Circuits and Systems II: Express Briefs, 57(5) (2010) 369-373.
[11] K. Monfaredi, Distributed Unique-Size MOS Technique: A Promising Universal Approach Capable of Resolving Circuit Design Bottlenecks of Modern Era, Circuits, Systems, and Signal Processing, (2018).
[12] S.M. McDonnell, V.J. Patel, L. Duncan, B. Dupaix, W. Khalil, Compensation and calibration techniques for current-steering DACs, IEEE Circuits and Systems Magazine, 17(2) (2017) 4-26.
[13] N. Pal, P. Nandi, R. Biswas, A.G. Katakwar, Placement-based nonlinearity reduction technique for differential current-steering DAC, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 24(1) (2016) 233-242.
[14] S. Saeedi, S. Mehrmanesh, M. Atarodi, A low voltage 14-bit self-calibrated CMOS DAC with enhanced dynamic linearity, Analog Integrated Circuits and Signal Processing, 43(2) (2005) 137-145.
[15] J. Pirkkalaniemi, M. Waltari, M. Kosunen, L. Sumanen, K. Halonen, A 14-bit current-steering DAC with current-mode deglitcher, Analog Integrated Circuits and Signal Processing, 35(1) (2003) 33-45.
[16] I. Myderrizi, A. Zeki, A high-speed swing reduced driver suitable for current-steering digital-to-analog converters, in: Circuit Theory and Design, 2009. ECCTD 2009. European Conference on, IEEE, 2009, pp. 635-638.
[17] A. van Roermund, M. Vertreg, D. Leenaerts, J. Briaire, K. Doris, A 12b 500MS/s DAC with> 70dB SFDR up to 120MHz in 0.18 μm CMOS, in: Solid-State Circuits Conference, 2005. Digest of Technical Papers. ISSCC. 2005 IEEE International, IEEE, 2005, pp. 116-588.
[18] P.G. Darji, C.D. Parikh, Novel Analog Calibration Technique for Current-Steering DACs, Circuits, Systems, and Signal Processing, 34(8) (2015) 2407-2418.
[19] P.G. Darji, C.D. Parikh, Novel Analog Calibration Technique for Current-Steering DACs’ Dynamic Performance, Circuits, Systems, and Signal Processing, 35(7) (2016) 2616-2625.
[20] K. Monfaredi, S. Jan Mohammadi, Dynamic foreground calibration of binary-weighted current-steering DAC, Iranian Journal of Science and Technology, Transactions of Electrical Engineering, 43 (2019) 699-716.
[21] S.J. Azhari, K. Monfaredi, S. Amiri, A 12-bit, low-voltage, nanoampere-based, ultralow-power, ultralow-glitch current-steering DAC for HDTV, International Nano Letters, 2(1) (2012) 35. | ||
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