پیوندهای مفید
آمار
| تعداد نشریات | 8 |
| تعداد شمارهها | 440 |
| تعداد مقالات | 5,679 |
| تعداد مشاهده مقاله | 7,810,323 |
| تعداد دریافت فایل اصل مقاله | 6,386,933 |
Studying the Impact of Technology Scaling on the Performance of MOSFET Devices Using Semi-Empirical Modeling Through the Inversion Coefficient | ||
| AUT Journal of Electrical Engineering | ||
| مقاله 5، دوره 57، شماره 3، 2025، صفحه 473-484 اصل مقاله (4.18 M) | ||
| نوع مقاله: Research Article | ||
| شناسه دیجیتال (DOI): 10.22060/eej.2025.24005.5646 | ||
| نویسندگان | ||
| Gholamreza Khademevatan؛ Ali Jalali* | ||
| Department of Electrical Engineering, Shahid Beheshti University, Tehran, Iran | ||
| چکیده | ||
| For six decades, integrated circuit design and manufacturing have fueled information technology's explosive growth, powering modern computing and advancing contemporary civilization. Advancements in this industry are primarily driven by the shrinking of technology and the reduction of transistor channel length in metal oxide semiconductor devices. This paper examines the impact of these factors on the characteristics and performance trade-offs of metal oxide semiconductor devices, focusing on the inversion coefficient as a key design parameter across all inversion regions (Weak Inversion, Moderate Inversion, and Strong Inversion). The performance trade-offs, analyzed in terms of inversion coefficient in 90nm and 180nm processes, encompass sizing relationships, DC bias and small signal parameters, gain and bandwidth, gate-referred thermal and flicker noise, DC mismatch, gate-source leakage and figure of merit for low-power radio frequency designs. Graphically displaying performance trends against inversion coefficient across two fabrication technologies allows for selection of desired trade-offs as the process is shrunk. Finally, an operating plane for metal oxide semiconductor devices is presented, enabling the selection of appropriate bias points to optimize device performance within the desired circuit as technology scales down. | ||
| کلیدواژهها | ||
| Metal Oxide Semiconductor؛ Inversion Coefficient؛ Weak Inversion؛ Moderate Inversion؛ Strong Inversion؛ Radio Frequency | ||
| مراجع | ||
|
[1] W. Cao, H. Bu, M. Vinet, M. Cao, S. Takagi, S. Hwang, T. Ghani, K. Banerjee, The future transistors, Nature, 620(7974) (2023) 501–515.
[2] H.H. Radamson, Y. Miao, Z. Zhou, Z. Wu, Z. Kong, J. Gao, H. Yang, Y. Ren, Y. Zhang, J. Shi, CMOS scaling for the 5 nm node and beyond: Device, process and technology, Nanomaterials, 14(10) (2024) 837.
[3] R.K. Ratnesh, A. Goel, G. Kaushik, H. Garg, M. Singh, B. Prasad, Advancement and challenges in MOSFET scaling, Materials Science in Semiconductor Processing, 134 (2021) 106002.
[4] A. Girardi, L. Compassi-Severo, P.C.C. de Aguirre, Design techniques for ultra-low voltage analog circuits using CMOS characteristic curves: A practical tutorial, Journal of Integrated Circuits and Systems, 17(1) (2022) 1–11.
[5] K. Singh, P. Jain, BSIM3v3 to EKV2. 6 Model Parameter Extraction and Optimisation using LM Algorithm on 0.18 μ Technology node, International Journal of Electronics and Telecommunications, 64(1) (2018) 5–11.
[6] K. Mistry, G. Grula, J. Sleight, L. Bai, R. Stephany, R. Flatley, P. Skerry, A 2.0 V, 0.35/spl mu/m partially depleted SOI-CMOS technology, in: International Electron Devices Meeting. IEDM Technical Digest, IEEE, 1997, pp. 583–586.
[7] B.M. Tenbroek, M.S. Lee, W. Redman-White, J.T. Bunyan, M.J. Uren, Self-heating effects in SOI MOSFETs and their measurement by small signal conductance techniques, IEEE Transactions on Electron Devices, 43(12) (1996) 2240–2248.
[8] K.J. Kuhn, Considerations for ultimate CMOS scaling, IEEE Transactions on Electron Devices, 59(7) (2012) 1813–1828.
[9] M.T. Bohr, R.S. Chau, T. Ghani, K. Mistry, The high-k solution, IEEE spectrum, 44(10) (2007) 29–35.
[10] W. Sansen, Biasing for zero distortion: Using the ekv\/bsim6 expressions, IEEE Solid-State Circuits Magazine, 10(3) (2018) 48–53.
[11] W. Sansen, Minimum power in analog amplifying blocks: Presenting a design procedure, IEEE Solid-State Circuits Magazine, 7(4) (2015) 83–89.
[12] C. Enz, F. Chicco, A. Pezzotta, Nanoscale MOSFET modeling: Part 2: Using the inversion coefficient as the primary design parameter, IEEE Solid-State Circuits Magazine, 9(4) (2017) 73–81.
[13] C. Enz, F. Chicco, A. Pezzotta, Nanoscale MOSFET modeling: Part 1: The simplified EKV model for the design of low-power analog circuits, IEEE Solid-State Circuits Magazine, 9(3) (2017) 26–35.
[14] T. Ghani, M. Armstrong, C. Auth, M. Bost, P. Charvat, G. Glass, T. Hoffmann, K. Johnson, C. Kenyon, J. Klaus, A 90nm high volume manufacturing logic technology featuring novel 45nm gate length strained silicon CMOS transistors, in: IEEE International Electron Devices Meeting 2003, IEEE, 2003, pp. 11.16. 11–11.16. 13.
[15] E.A. Vittoz, Micropower techniques, Design of VLSI circuits for telecommunication and signal processing, (1994) 53–97.
[16] C.C. Enz, F. Krummenacher, E.A. Vittoz, An analytical MOS transistor model valid in all regions of operation and dedicated to low-voltage and low-current applications, Analog integrated circuits and signal processing, 8(1) (1995) 83–114.
[17] G. Khademevatan, A. Jalali, Inversion Coefficient as a Key Design Parameter in MOS Device Performance, in: 2024 32nd International Conference on Electrical Engineering (ICEE), IEEE, 2024, pp. 1–7.
[18] G. Khademevatan, A. Jalali, Study of linearity indices in analog/RF circuits using EKV model and comparing the results in three different CMOS processes, in: 2022 Iranian International Conference on Microelectronics (IICM), IEEE, 2022, pp. 1–7.
[19] C. Auth, C. Allen, A. Blattner, D. Bergstrom, M. Brazier, M. Bost, M. Buehler, V. Chikarmane, T. Ghani, T. Glassman, A 22nm high-performance and low-power CMOS technology featuring fully-depleted tri-gate transistors, self-aligned contacts and high-density MIM capacitors, in: 2012 symposium on VLSI technology (VLSIT), IEEE, 2012, pp. 131–132.
[20] K. Mistry, C. Allen, C. Auth, B. Beattie, D. Bergstrom, M. Bost, M. Brazier, M. Buehler, A. Cappellani, R. Chau, A 45nm logic technology with high-k+ metal gate transistors, strained silicon, 9 Cu interconnect layers, 193nm dry patterning, and 100% Pb-free packaging, in: 2007 IEEE international electron devices meeting, IEEE, 2007, pp. 247–250.
[21] W.G. Tuni, Design Methodology of Analog and RF Building Blocks Based on Precomputed Actual Device Technology Data, University of Florida, 2020.
[22] B. Razavi, RF Microelectronics (2nd Edition) (Prentice Hall Communications Engineering and Emerging Technologies Series), Prentice Hall Press, 2011.
[23] IC LAB of EPFL University, EKV MOSFET MODEL, in, April. 30, 2024.
[24] G. Guitton, Design Methodologies for multi-mode and multi-standard Low-Noise Amplifiers, Université de Bordeaux, 2017.
[25] C.C. Enz, E.A. Vittoz, Charge-based MOS transistor modeling: the EKV model for low-power and RF IC design, John Wiley & Sons, 2006.
[26] D. Binkley, Tradeoffs and Optimization in Analog CMOS Design, John Wiley & Sons, Limited, 2008. | ||
|
آمار تعداد مشاهده مقاله: 203 تعداد دریافت فایل اصل مقاله: 116 |
||