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Cascaded Multilevel Inverters with Reduced Structures Based on a Recently Proposed Basic Units: Implementing a 147-level Inverter | ||
| AUT Journal of Electrical Engineering | ||
| مقاله 4، دوره 49، شماره 2، اسفند 2017، صفحه 141-150 اصل مقاله (1.59 M) | ||
| نوع مقاله: Research Article | ||
| شناسه دیجیتال (DOI): 10.22060/eej.2017.11432.4967 | ||
| نویسندگان | ||
| M. J. Mojibian* 1؛ M. Tavakoli Bina1؛ B. Eskandari2 | ||
| 1Department of Electrical Engineering, K. N. Toosi University of Technology, Tehran, Iran | ||
| 2Department of Electrical Engineering, Malayer University, Malayer, Iran | ||
| چکیده | ||
| A multilevel inverter is capable of generating high-quality stepwise pseudo-sinusoidal voltage with low THD , applicable to high-power and high-voltage systems. These types of topologies may require a large number of switches and power supplies. This leads to much cost, large size, and complicated control algorithms. Thus, newer topologies are being proposed to decrease the number of power electronic devices for a large number of levels in output voltage. Recently, a new multilevel inverter has been reported in the literature to reduce component count. Its structure requires a lower number of active switches as compared to the existing ones. The available literature presents a generalization of the topology with an especial asymmetrical sources ratio, but no investigations are made for other symmetrical or asymmetrical sources ratio with cascaded configurations. This study presents a comprehensive analysis of cascaded topologies with the proposed basic units. The topology is analysed for both symmetric and asymmetric DC source configurations. Also, two algorithms for asymmetric source configuration suitable for cascaded structures are proposed. Moreover, the design and simulation of a 147-level inverter are presented under an optimal number of DC sources and power switches. Furthermore, experimental validation is performed by implementing a laboratory prototype. | ||
| کلیدواژه‌ها | ||
| Asymmetrical DC Sources؛ Multilevel Inverter؛ Packed U cell؛ Reduced Structures | ||
| مراجع | ||
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